The present invention relates to racetrack memory devices, and more specifically, to racetrack memory cells having vertical nanowire storage elements.
Racetrack memory is a type of non-volatile magnetic memory that utilizes current-controlled motion of magnetic domain walls in a magnetic nanowire to encode information. Multiple magnetic domain walls can be moved along the nanowire “racetrack.” In typical configurations, a magnetic tunnel junction (MTJ) is located at a distinct location along the track; the MTJ is used to read out the device by sensing the magnetization of the nanowire as domain walls shift through the nanowire.
Typical configurations implement in-plane nanowires, horizontally positioned with respect to the wafer plane. It had been theorized that to achieve very high bit density, the ideal racetrack memory cell would have the racetrack nanowire oriented perpendicular to the wafer plane. Devices with such vertically oriented racetracks are extremely challenging to build, and there have been proposals for vertical racetrack cells but few structures proposed that have any specific details about the structure or fabrication methods, and no practical method proposed to integrate an MTJ for readout. Furthermore, integration of an MTJ in direct contact with the nanowire is challenging even in planar-nanowire configurations, because it often introduces process defects that lead to pinning of the domain walls at the site of the MTJ. To date there is no known fabrication method for vertical nanowires.